Hardware Implementation of Real-time NLM algorithm

Gongyu Fan*, Wenbiao Zhou, Fengchi Lu, Boyu Zhu, Yongxiang Zhou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Recent years, Image Signal Processor (ISP) has been wildly used in our daily lives. Non-local means (NLM) is one of the most robust noise reduction algorithms, but its computational complexity makes it difficult to be used for the real-time processing. In this paper, we propose a hardware implementation of real-time NLM algorithm and discuss some details of the implementation. Eventually we synthesized and implemented it on an FPGA to analyze the resource utilization and the performance and draw some common conclusions.

Original languageEnglish
Title of host publicationFourth International Conference on Algorithms, Microchips, and Network Applications, AMNA 2025
EditorsJavid Taheri, Lei Chen
PublisherSPIE
ISBN (Electronic)9781510690608
DOIs
Publication statusPublished - 2025
Event4th International Conference on Algorithms, Microchips, and Network Applications, AMNA 2025 - Yangzhou, China
Duration: 7 Mar 20259 Mar 2025

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume13576
ISSN (Print)0277-786X
ISSN (Electronic)1996-756X

Conference

Conference4th International Conference on Algorithms, Microchips, and Network Applications, AMNA 2025
Country/TerritoryChina
CityYangzhou
Period7/03/259/03/25

Keywords

  • FPGA
  • ISP
  • Non-Local Means
  • hardware implementation
  • real-time

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